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CODES
2007
IEEE
15 years 8 months ago
Event-based re-training of statistical contention models for heterogeneous multiprocessors
Embedded single-chip heterogeneous multiprocessor (SCHM) systems experience frequent system events such as task preemption, power-saving voltage/frequency scaling, or arrival of n...
Alex Bobrek, JoAnn M. Paul, Donald E. Thomas
113
Voted
CODES
2007
IEEE
15 years 8 months ago
Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip
Networks on Chip (NoC) have emerged as the design paradigm for scalable System on Chip communication infrastructure. A growing number of applications, often with firm (FRT) or so...
Andreas Hansson, Martijn Coenen, Kees Goossens
135
Voted
CODES
2007
IEEE
15 years 8 months ago
Three-dimensional multiprocessor system-on-chip thermal optimization
3D stacked wafer integration has the potential to improve multiprocessor system-on-chip (MPSoC) integration density, performance, and power efficiency. However, the power density...
Chong Sun, Li Shang, Robert P. Dick
CODES
2007
IEEE
15 years 8 months ago
Performance modeling for early analysis of multi-core systems
Performance analysis of microprocessors is a critical step in defining the microarchitecture, prior to register-transfer-level (RTL) design. In complex chip multiprocessor systems...
Reinaldo A. Bergamaschi, Indira Nair, Gero Dittman...
129
Voted
CODES
2007
IEEE
15 years 8 months ago
A code-generator generator for multi-output instructions
We address the problem of instruction selection for Multi-Output Instructions (MOIs), producing more than one result. Such inherently parallel hardware instructions are very commo...
Hanno Scharwächter, Jonghee M. Youn, Rainer L...
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