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» Engineering parallel applications with tunable architectures
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SASP
2008
IEEE
183views Hardware» more  SASP 2008»
14 years 1 months ago
Application Acceleration with the Explicitly Parallel Operations System - the EPOS Processor
Different approaches have been proposed over the years for automatically transforming High-Level-Languages (HLL) descriptions of applications into custom hardware implementations. ...
Alexandros Papakonstantinou, Deming Chen, Wen-mei ...
SC
2009
ACM
14 years 2 months ago
Kepler + Hadoop: a general architecture facilitating data-intensive applications in scientific workflow systems
MapReduce provides a parallel and scalable programming model for data-intensive business and scientific applications. MapReduce and its de facto open source project, called Hadoop...
Jianwu Wang, Daniel Crawl, Ilkay Altintas
ICMCS
2007
IEEE
159views Multimedia» more  ICMCS 2007»
14 years 1 months ago
Accelerating Mutual-Information-Based Linear Registration on the Cell Broadband Engine Processor
Emerging multi-core processors are able to accelerate medical imaging applications by exploiting the parallelism available in their algorithms. We have implemented a mutual-inform...
Moriyoshi Ohara, Hangu Yeo, Frank Savino, Giridhar...
DEBS
2010
ACM
13 years 11 months ago
Evaluation of streaming aggregation on parallel hardware architectures
We present a case study parallelizing streaming aggregation on three different parallel hardware architectures. Aggregation is a performance-critical operation for data summarizat...
Scott Schneider, Henrique Andrade, Bugra Gedik, Ku...
VLSISP
1998
128views more  VLSISP 1998»
13 years 7 months ago
A Low Power DSP Engine for Wireless Communications
This paper describes the architecture and the performance of a new programmable 16-bit Digital Signal Processor (DSP) engine. It is developed specifically for next generation wire...
Ingrid Verbauwhede, Mihran Touriguian