Sciweavers

528 search results - page 69 / 106
» Epistemic Logic and Planning
Sort
View
ASPDAC
2008
ACM
104views Hardware» more  ASPDAC 2008»
13 years 9 months ago
Low power clock buffer planning methodology in F-D placement for large scale circuit design
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xian...
WSC
2007
13 years 10 months ago
Modeling and simulation for customer driven manufacturing system design and operations planning
Agility, speed and flexibility in production networks are required in today's global competition in the flat world. The accuracy of order date delivery promises is a key elem...
Juhani Heilala, Jari Montonen, Arttu Salmela, Pasi...
ATAL
2009
Springer
14 years 2 months ago
Abstraction in model checking multi-agent systems
ion in model checking multi-agent systems Mika Cohen Department of Computing Imperial College London London, UK Mads Dam Access Linnaeus Center Royal Institute of Technology Stockh...
Mika Cohen, Mads Dam, Alessio Lomuscio, Francesco ...
AI
2004
Springer
13 years 7 months ago
ASSAT: computing answer sets of a logic program by SAT solvers
We propose a new translation from normal logic programs with constraints under the answer set semantics to propositional logic. Given a normal logic program, we show that by addin...
Fangzhen Lin, Yuting Zhao
LANMR
2004
13 years 9 months ago
New Semantics for Hybrid Probabilistic Programs
Hybrid probabilistic programs framework [5] is a variation of probabilistic annotated logic programming approach, which allows the user to explicitly encode the available knowledge...
Emad Saad