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» Evaluating CMPs and Their Memory Architecture
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EUROSYS
2009
ACM
14 years 4 months ago
Pointless tainting?: evaluating the practicality of pointer tainting
This paper evaluates pointer tainting, an incarnation of Dynamic Information Flow Tracking (DIFT), which has recently become an important technique in system security. Pointer tai...
Asia Slowinska, Herbert Bos
ASPLOS
2009
ACM
14 years 2 months ago
Architectural implications of nanoscale integrated sensing and computing
This paper explores the architectural implications of integrating computation and molecular probes to form nanoscale sensor processors (nSP). We show how nSPs may enable new compu...
Constantin Pistol, Christopher Dwyer, Alvin R. Leb...
HASE
2007
IEEE
14 years 2 months ago
Systems Architectures for Transactional Network Interface
Systems such as software transactional memory and some exception handling techniques use transactions. However, a typical limitation of such systems is that they do not allow syst...
Manish Marwah, Shivakant Mishra, Christof Fetzer
GLOBECOM
2006
IEEE
14 years 1 months ago
Scalable Layer-2/Layer-3 Multistage Switching Architectures for Software Routers
Abstract— Software routers are becoming an important alternative to proprietary and expensive network devices, because they exploit the economy of scale of the PC market and open...
Andrea Bianco, Jorge M. Finochietto, Giulio Galant...
HPCA
2009
IEEE
14 years 8 months ago
In-Network Snoop Ordering (INSO): Snoopy coherence on unordered interconnects
Realizing scalable cache coherence in the many-core era comes with a whole new set of constraints and opportunities. It is widely believed that multi-hop, unordered on-chip networ...
Niket Agarwal, Li-Shiuan Peh, Niraj K. Jha