501 search results - page 69 / 101 » Evaluating CMPs and Their Memory Architecture |
IPPS
2009
IEEE
14 years 2 months ago
2009
IEEE
In this paper we explore the impact of the block shape on blocked and vectorized versions of the Sparse Matrix-Vector Multiplication (SpMV) kernel and build upon previous work by ...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
Step caches are caches in which data entered to an cache array is kept valid only until the end of ongoing step of execution. Together with an advanced pipelined multithreaded arc...
ISHPC
1997
Springer
13 years 11 months ago
1997
Springer
We propose two resource management methods; a scheduling policy that re
ects resource consumption states and a memory-replacement strategy based on page classi cation under distrib...
VLDB
1999
ACM
13 years 12 months ago
1999
ACM
Recent high-performance processors employ sophisticated techniques to overlap and simultaneously execute multiple computation and memory operations. Intuitively, these techniques ...
EUROSYS
2007
ACM
14 years 4 months ago
2007
ACM
In most modern operating systems, a process is a -protected abstraction for isolating code and data. This protection, however, is selective. Many common mechanisms—dynamic code ...