501 search results - page 89 / 101 » Evaluating CMPs and Their Memory Architecture |
SBACPAD
2003
IEEE
14 years 27 days ago
2003
IEEE
In this paper, we reevaluate the use of adaptive compressed caching to improve system performance through the reduction of accesses to the backing stores. We propose a new adaptab...
MSE
2002
IEEE
14 years 16 days ago
2002
IEEE
This paper presents the study of running several core multimedia applications on a simultaneous multithreading (SMT) architecture and derives design principles for multimedia soft...
PLDI
1999
ACM
13 years 12 months ago
1999
ACM
This paper explores compiler techniques for reducing the memory needed to load and run program executables. In embedded systems, where economic incentives to reduce both ram and r...
APN
1999
Springer
13 years 12 months ago
1999
Springer
Abstract. This paper presents parallel approaches to the complete transient numerical analysis of stochastic reward nets (SRNs) for both shared and distributed-memory machines. Par...
IPCCC
1999
IEEE
13 years 12 months ago
1999
IEEE
Many computer hardware and software architectures buffer data in memory to improve system performance. Volatile disk or file caches are sometimes used to delay the propagation of ...