1304 search results - page 107 / 261 » Evaluating Hardware Compilation Techniques |
138
Voted
PLDI
2000
ACM
15 years 9 months ago
2000
ACM
We describe the design and implementation of Dynamo, a software dynamic optimization system that is capable of transparently improving the performance of a native instruction stre...
133
Voted
CAINE
2006
15 years 6 months ago
2006
The synergy of software and hardware leads to efficient application expression profile (AEP) not only in terms of execution time and energy but also optimal architecture usage. We...
135
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ISLPED
1995
ACM
15 years 8 months ago
1995
ACM
The need to reduce the power consumption of the next generation of digital systems is clearly recognized. At the system level, power management is a very powerful technique and de...
138
Voted
CG
2007
Springer
15 years 4 months ago
2007
Springer
With the availability of pen-enabled digital hardware, sketch-based 3D modeling is becoming an increasingly attractive alternative to traditional methods in many design environmen...
133
Voted
ISCA
1999
IEEE
15 years 8 months ago
1999
IEEE
Modern compilers must expose sufficient amounts of Instruction-Level Parallelism (ILP) to achieve the promised performance increases of superscalar and VLIW processors. One of the...