1304 search results - page 42 / 261 » Evaluating Hardware Compilation Techniques |
FPL
2008
Springer
13 years 11 months ago
2008
Springer
The power consumption of Dynamically Reconfigurable Processing Array (DRPA) is quantitatively analyzed by using a real chip layout and applications taking into account the reconfi...
SC
1992
ACM
14 years 2 months ago
1992
ACM
Exploiting parallelism at both the multiprocessor level and the instruction level is an e ective means for supercomputers to achieve high-performance. The amount of instruction-le...
CC
2009
Springer
14 years 4 months ago
2009
Springer
Software systems typically exploit only a small fraction of the realizable performance from the underlying microprocessors. While there has been much work on hardware-aware optimiz...
JUCS
2000
13 years 9 months ago
2000
: Since the era of vector and pipelined computing, the computational speed is limited by the memory access time. Faster caches and more cache levels are used to bridge the growing ...
IEEEPACT
1997
IEEE
14 years 2 months ago
1997
IEEE
† In this paper, we propose a parallel randomized algorithm, called Parallel Fast Assignment using Search Technique (PFAST), for scheduling parallel programs represented by direc...