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» Evaluating Hardware Compilation Techniques
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ISSS
1996
IEEE
143views Hardware» more  ISSS 1996»
13 years 11 months ago
DSP Processor/Compiler Co-Design: A Quantitative Approach
In the paper the problem of processor/compiler codesign for digital signal processing and embedded SYstems is discussed. The main principle we follow is the top-down approach char...
Vojin Zivojnovic, Stefan Pees, C. Schälger, M...
DSN
2003
IEEE
14 years 29 days ago
Compiler-Directed Program-Fault Coverage for Highly Available Java Internet Services
Abstract: We present a new approach that uses compilerdirected fault-injection for coverage testing of recovery code in Internet services to evaluate their robustness to operating ...
Chen Fu, Richard P. Martin, Kiran Nagaraja, Thu D....
CGO
2010
IEEE
14 years 24 days ago
Taming hardware event samples for FDO compilation
Feedback-directed optimization (FDO) is effective in improving application runtime performance, but has not been widely adopted due to the tedious dual-compilation model, the difï...
Dehao Chen, Neil Vachharajani, Robert Hundt, Shih-...
PLDI
1997
ACM
13 years 12 months ago
Two for the Price of One: Composing Partial Evaluation and Compilation
One of the flagship applications of partial evaluation is compilation and compiler generation. However, partial evaluation is usually expressed as a source-to-source transformati...
Michael Sperber, Peter Thiemann
CASES
2006
ACM
13 years 11 months ago
Incremental elaboration for run-time reconfigurable hardware designs
We present a new technique for compiling run-time reconfigurable hardware designs. Run-time reconfigurable embedded systems can deliver promising benefits over implementations in ...
Arran Derbyshire, Tobias Becker, Wayne Luk