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» Evaluating Statistical Power Optimization
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FPGA
2007
ACM
185views FPGA» more  FPGA 2007»
14 years 3 months ago
Power-aware FPGA logic synthesis using binary decision diagrams
Power consumption in field programmable gate arrays (FPGAs) has become an important issue as the FPGA market has grown to include mobile platforms. In this work we present a power...
Kevin Oo Tinmaung, David Howland, Russell Tessier
GLVLSI
2010
IEEE
156views VLSI» more  GLVLSI 2010»
14 years 2 months ago
A multi-level approach to reduce the impact of NBTI on processor functional units
NBTI is one of the most important silicon reliability problems facing processor designers today. The impact of NBTI can be mitigated at both the circuit and microarchitecture leve...
Taniya Siddiqua, Sudhanva Gurumurthi
CODES
2004
IEEE
14 years 1 months ago
Compiler-directed code restructuring for reducing data TLB energy
Prior work on TLB power optimization considered circuit and architectural techniques. A recent software-based technique for data TLBs has considered the possibility of storing the...
Mahmut T. Kandemir, Ismail Kadayif, Guilin Chen
CDES
2006
136views Hardware» more  CDES 2006»
13 years 11 months ago
CMOL FPGA circuits
Abstract--This paper describes an architecture of FPGAlike fabric for future hybrid "CMOL" circuits. Such circuits will combine a semiconductor-transistor (CMOS) stack an...
Dmitri B. Strukov, Konstantin Likharev
ISCA
2012
IEEE
234views Hardware» more  ISCA 2012»
12 years 3 days ago
PARDIS: A programmable memory controller for the DDRx interfacing standards
Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource...
Mahdi Nazm Bojnordi, Engin Ipek