38 search results - page 5 / 8 » Evaluating Techniques for Exploiting Instruction Slack |
DASFAA
2007
IEEE
14 years 1 months ago
2007
IEEE
In the era of the Internet, more and more privacy-sensitive data is published online. Even though this kind of data are published with sensitive attributes such as name and social ...
SAMOS
2004
Springer
14 years 22 days ago
2004
Springer
— Architectural resources and program recurrences are the main limitations to the amount of Instruction-Level Parallelism (ILP) exploitable from loops, the most time-consuming pa...
ICPP
2008
IEEE
14 years 1 months ago
2008
IEEE
The issue queue (IQ) is a key microarchitecture structure for exploiting instruction-level and thread-level parallelism in dynamically scheduled simultaneous multithreaded (SMT) p...
ICS
1995
Tsinghua U.
13 years 11 months ago
1995
Tsinghua U.
Modulo scheduling is an e cient technique for exploiting instruction level parallelism in a variety of loops, resulting in high performance code but increased register requirement...
AIED
2007
Springer
14 years 1 months ago
2007
Springer
Good teachers know their students, and exploit this knowledge to adapt or optimise their instruction. Traditional teachers know their students because they interact with them face-...