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ISCA
2002
IEEE
95views Hardware» more  ISCA 2002»
14 years 1 months ago
An Instruction Set and Microarchitecture for Instruction Level Distributed Processing
An instruction set architecture (ISA) suitable for future microprocessor design constraints is proposed. The ISA has hierarchical register files with a small number of accumulator...
Ho-Seop Kim, James E. Smith
ACSC
2003
IEEE
14 years 1 months ago
Communication Performance Issues for Two Cluster Computers
Clusters of commodity machines have become a popular way of building cheap high performance parallel computers. Many of these designs rely on standard Ethernet networks as a syste...
Francis Vaughan, Duncan A. Grove, Paul D. Coddingt...
IPPS
1997
IEEE
14 years 21 days ago
An Architecture Workbench for Multicomputers
The large design space of modern computer architectures calls for performance modelling tools to facilitate the evaluation of different alternatives. In this paper, we give an ove...
Andy D. Pimentel, Louis O. Hertzberger
ICS
1993
Tsinghua U.
14 years 18 days ago
The EM-4 Under Implicit Parallelism
: The EM-4 is a supercomputer that offers very fast inter processor communication and support for multi threading. In this paper we demonstrate that the EM-4, Together with an auto...
Lubomir Bic, Mayez A. Al-Mouhamed
ICS
2004
Tsinghua U.
14 years 1 months ago
Evaluating support for global address space languages on the Cray X1
The Cray X1 was recently introduced as the first in a new line of parallel systems to combine high-bandwidth vector processing with an MPP system architecture. Alongside capabili...
Christian Bell, Wei-Yu Chen, Dan Bonachea, Katheri...