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ICECCS
2010
IEEE
196views Hardware» more  ICECCS 2010»
13 years 8 months ago
Implementing and Evaluating a Model Checker for Transactional Memory Systems
Abstract—Transactional Memory (TM) is a promising technique that addresses the difficulty of parallel programming. Since TM takes responsibility for all concurrency control, TM ...
Woongki Baek, Nathan Grasso Bronson, Christos Kozy...
CODES
1996
IEEE
13 years 12 months ago
Partitioning and Exploration Strategies in the TOSCA Co-Design Flow
The TaSCA environment for hardware/software co-design of control dominated systems implemented on a single chip includes a novel approach to the system exploration phase for the e...
Alessandro Balboni, William Fornaciari, Donatella ...
ICDE
2010
IEEE
178views Database» more  ICDE 2010»
13 years 8 months ago
Autonomic workload execution control using throttling
— Database Management Systems (DBMSs) are often required to simultaneously process multiple diverse workloads while enforcing business policies that govern workload performance. ...
Wendy Powley, Patrick Martin, Mingyi Zhang, Paul B...
IPM
2006
75views more  IPM 2006»
13 years 7 months ago
Performance of query processing implementations in ranking-based text retrieval systems using inverted indices
Similarity calculations and document ranking form the computationally expensive parts of query processing in ranking-based text retrieval. In this work, for these calculations, 11...
Berkant Barla Cambazoglu, Cevdet Aykanat
ISCA
2012
IEEE
234views Hardware» more  ISCA 2012»
11 years 10 months ago
PARDIS: A programmable memory controller for the DDRx interfacing standards
Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource...
Mahdi Nazm Bojnordi, Engin Ipek