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ISCA
2009
IEEE
189views Hardware» more  ISCA 2009»
14 years 2 months ago
Hybrid cache architecture with disparate memory technologies
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ra...
OOPSLA
2009
Springer
14 years 2 months ago
Scalable nonblocking concurrent objects for mission critical code
The high degree of complexity and autonomy of future robotic space missions, such as Mars Science Laboratory (MSL), poses serious challenges in assuring their reliability and efï¬...
Damian Dechev, Bjarne Stroustrup
EMSOFT
2008
Springer
13 years 8 months ago
On the interplay of dynamic voltage scaling and dynamic power management in real-time embedded applications
Dynamic Voltage Scaling (DVS) and Dynamic Power Management (DPM) are two popular techniques commonly employed to save energy in real-time embedded systems. DVS policies aim at red...
Vinay Devadas, Hakan Aydin
ISLPED
2010
ACM
231views Hardware» more  ISLPED 2010»
13 years 8 months ago
3D-nonFAR: three-dimensional non-volatile FPGA architecture using phase change memory
Memories play a key role in FGPAs in the forms of both programming bits and embedded memory blocks. FPGAs using non-volatile memories have been the focus of attention with zero bo...
Yibo Chen, Jishen Zhao, Yuan Xie
HOTNETS
2010
13 years 2 months ago
Packet re-cycling: eliminating packet losses due to network failures
This paper presents Packet Re-cycling (PR), a technique that takes advantage of cellular graph embeddings to reroute packets that would otherwise be dropped in case of link or nod...
Suksant Sae Lor, Raul Landa, Miguel Rio