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PDP
2011
IEEE
12 years 11 months ago
Quantifying Thread Vulnerability for Multicore Architectures
Abstract—Continuously reducing transistor sizes and aggressive low power operating modes employed by modern architectures tend to increase transient error rates. Concurrently, mu...
Isil Oz, Haluk Rahmi Topcuoglu, Mahmut T. Kandemir...
IVA
2009
Springer
14 years 2 months ago
Teaching Computers to Conduct Spoken Interviews: Breaking the Realtime Barrier with Learning
Abstract. Several challenges remain in the effort to build software capable of conducting realtime dialogue with people. Part of the problem has been a lack of realtime flexibili...
Gudny Ragna Jonsdottir, Kristinn R. Thóriss...
HIPEAC
2009
Springer
14 years 6 days ago
Steal-on-Abort: Improving Transactional Memory Performance through Dynamic Transaction Reordering
Abstract. In transactional memory, aborted transactions reduce performance, and waste computing resources. Ideally, concurrent execution of transactions should be optimally ordered...
Mohammad Ansari, Mikel Luján, Christos Kots...
ICS
2009
Tsinghua U.
14 years 2 months ago
Towards 100 gbit/s ethernet: multicore-based parallel communication protocol design
Ethernet line rates are projected to reach 100 Gbits/s by as soon as 2010. While in principle suitable for high performance clustered and parallel applications, Ethernet requires ...
Stavros Passas, Kostas Magoutis, Angelos Bilas
ACSAC
2006
IEEE
14 years 1 months ago
Address Space Layout Permutation (ASLP): Towards Fine-Grained Randomization of Commodity Software
Address space randomization is an emerging and promising method for stopping a broad range of memory corruption attacks. By randomly shifting critical memory regions at process in...
Chongkyung Kil, Jinsuk Jun, Christopher Bookholt, ...