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» Event-driven processor power management
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ICS
2007
Tsinghua U.
14 years 1 months ago
Automatic nonblocking communication for partitioned global address space programs
Overlapping communication with computation is an important optimization on current cluster architectures; its importance is likely to increase as the doubling of processing power ...
Wei-Yu Chen, Dan Bonachea, Costin Iancu, Katherine...
PPOPP
2006
ACM
14 years 1 months ago
McRT-STM: a high performance software transactional memory system for a multi-core runtime
Applications need to become more concurrent to take advantage of the increased computational power provided by chip level multiprocessing. Programmers have traditionally managed t...
Bratin Saha, Ali-Reza Adl-Tabatabai, Richard L. Hu...
ISLPED
2004
ACM
157views Hardware» more  ISLPED 2004»
14 years 1 months ago
4T-decay sensors: a new class of small, fast, robust, and low-power, temperature/leakage sensors
We present a novel temperature/leakage sensor, developed for high-speed, low-power, monitoring of processors and complex VLSI chips. The innovative idea is the use of 4T SRAM cell...
Stefanos Kaxiras, Polychronis Xekalakis
RTAS
1997
IEEE
13 years 12 months ago
QoS Negotiation in Real-Time Systems and Its Application to Automated Flight Control
ÐReal-time middleware services must guarantee predictable performance under specified load and failure conditions, and ensure graceful degradation when these conditions are violat...
Tarek F. Abdelzaher, Ella M. Atkins, Kang G. Shin
CF
2005
ACM
13 years 9 months ago
A case for a working-set-based memory hierarchy
Modern microprocessor designs continue to obtain impressive performance gains through increasing clock rates and advances in the parallelism obtained via micro-architecture design...
Steve Carr, Soner Önder