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ICS
1999
Tsinghua U.
13 years 11 months ago
Classifying load and store instructions for memory renaming
Memory operations remain a significant bottleneck in dynamically scheduled pipelined processors, due in part to the inability to statically determine the existence of memory addr...
Glenn Reinman, Brad Calder, Dean M. Tullsen, Gary ...
ICC
2008
IEEE
126views Communications» more  ICC 2008»
14 years 1 months ago
Backlog Aware Scheduling for Large Buffered Crossbar Switches
—A novel architecture was proposed in [1] to address scalability issues in large, high speed packet switches. The architecture proposed in [1], namely OBIG (output buffers with i...
Aditya Dua, Benjamin Yolken, Nicholas Bambos, Wlad...
JSA
2000
115views more  JSA 2000»
13 years 7 months ago
Scheduling optimization through iterative refinement
Scheduling DAGs with communication times is the theoretical basis for achieving efficient parallelism on distributed memory systems. We generalize Graham's task-level in a ma...
Mayez A. Al-Mouhamed, Adel Al-Massarani
PDP
2010
IEEE
13 years 11 months ago
hwloc: A Generic Framework for Managing Hardware Affinities in HPC Applications
The increasing numbers of cores, shared caches and memory nodes within machines introduces a complex hardware topology. High-performance computing applications now have to carefull...
François Broquedis, Jérôme Cle...
EUROPAR
2008
Springer
13 years 9 months ago
MPC: A Unified Parallel Runtime for Clusters of NUMA Machines
Over the last decade, Message Passing Interface (MPI) has become a very successful parallel programming environment for distributed memory architectures such as clusters. However, ...
Marc Pérache, Hervé Jourdren, Raymon...