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DSD
2010
IEEE
162views Hardware» more  DSD 2010»
13 years 6 months ago
A Parallel for Loop Memory Template for a High Level Synthesis Compiler
—We propose a parametrized memory template for applications with parallel for loops. The template’s parameters reflect important trade-offs made during system design. The temp...
Craig Moore, Wim Meeus, Harald Devos, Dirk Strooba...
ECCC
2010
143views more  ECCC 2010»
13 years 5 months ago
Space-Efficient Algorithms for Reachability in Surface-Embedded Graphs
We consider the reachability problem for a certain class of directed acyclic graphs embedded on surfaces. Let G(m, g) be the class of directed acyclic graphs with m = m(n) source ...
Derrick Stolee, N. V. Vinodchandran
DATE
2003
IEEE
118views Hardware» more  DATE 2003»
14 years 1 months ago
Multi-Granularity Metrics for the Era of Strongly Personalized SOCs
This paper details the first step of the Design Trotter framework for design space exploration applied to dedicated SOCs. The aim of this step is to provide metrics in order to gu...
Yannick Le Moullec, Nahla Ben Amor, Jean-Philippe ...
AC
2005
Springer
13 years 8 months ago
Software model checking with SPIN
The aim of this chapter is to give an overview of the theoretical foundation and the practical application of logic model checking techniques for the verification of multi-threade...
Gerard J. Holzmann
JRTIP
2008
249views more  JRTIP 2008»
13 years 8 months ago
Model-based mapping of reconfigurable image registration on FPGA platforms
Abstract Image registration is a computationally intensive application in the medical imaging domain that places stringent requirements on performance and memory management efficie...
Mainak Sen, Yashwanth Hemaraj, William Plishker, R...