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ICCAD
1998
IEEE
116views Hardware» more  ICCAD 1998»
13 years 11 months ago
On primitive fault test generation in non-scan sequential circuits
A method is presented for identifying primitive path-delay faults in non-scan sequential circuits and generating robust tests for all robustly testable primitive faults. It uses t...
Ramesh C. Tekumalla, Premachandran R. Menon
DATE
1998
IEEE
92views Hardware» more  DATE 1998»
13 years 11 months ago
Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques
A new approach for sequential circuit test generation is proposed that combines software testing based techniques at the high level with test enhancement techniques at the gate le...
Elizabeth M. Rudnick, Roberto Vietti, Akilah Ellis...
ICCAD
1998
IEEE
122views Hardware» more  ICCAD 1998»
13 years 11 months ago
Dynamic fault collapsing and diagnostic test pattern generation for sequential circuits
In this paper, we present results for significantly improving the performance of sequential circuit diagnostic test pattern generation (DATPG). Our improvements are achieved by de...
Vamsi Boppana, W. Kent Fuchs
ICCAD
1997
IEEE
147views Hardware» more  ICCAD 1997»
13 years 11 months ago
Built-in test generation for synchronous sequential circuits
We consider the problem of built-in test generation for synchronous sequential circuits. The proposed scheme leaves the circuit flip-flops unmodified, and thus allows at-speed ...
Irith Pomeranz, Sudhakar M. Reddy
DATE
1997
IEEE
109views Hardware» more  DATE 1997»
13 years 10 months ago
Sequential circuit test generation using dynamic state traversal
A new method for state justi cation is proposed for sequential circuit test generation. The linear list of states dynamically obtained during the derivation of test vectors is use...
Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. P...