307 search results - page 60 / 62 » Exception Handling: An Architecture Model and Utility Suppor... |
HPCA
2011
IEEE
12 years 11 months ago
2011
IEEE
Future CMPs will combine many simple cores with deep cache hierarchies. With more cores, cache resources per core are fewer, and must be shared carefully to avoid poor utilization...
MSWIM
2003
ACM
14 years 24 days ago
2003
ACM
The seamless communication of data and voice over short-range, point-to-multipoint wireless links between mobile and/or stationary devices is becoming a reality by newly introduce...
GAMESEC
2011
12 years 7 months ago
2011
Recent smartphones incorporate embedded GPS devices that enable users to obtain geographic information about their surroundings by providing a location-based service (LBS) with the...
NPL
2006
13 years 7 months ago
2006
The authors previously proposed a self-organizing Hierarchical Cerebellar Model Articulation Controller (HCMAC) neural network containing a hierarchical GCMAC neural network and a ...
PPOPP
2010
ACM
14 years 2 months ago
2010
ACM
To fully exploit multicore processors, applications are expected to provide a large degree of thread-level parallelism. While adequate for low core counts and their typical worklo...