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IPPS
1997
IEEE
13 years 11 months ago
A Reliable Hardware Barrier Synchronization Scheme
Barrier synchronization is a crucial operation for parallel systems. Many schemes have been proposed in the literature to achieve fast barrier synchronization through software, ha...
Rajeev Sivaram, Craig B. Stunkel, Dhabaleswar K. P...
IMC
2004
ACM
14 years 24 days ago
Introducing scalability in network measurement: toward 10 Gbps with commodity hardware
The capacity of today's network links, along with the heterogeneity of their traffic, is rapidly growing, more than the workstation’s processing power. This makes the task ...
Loris Degioanni, Gianluca Varenni
CODES
2006
IEEE
14 years 1 months ago
Challenges in exploitation of loop parallelism in embedded applications
Embedded processors have been increasingly exploiting hardware parallelism. Vector units, multiple processors or cores, hyper-threading, special-purpose accelerators such as DSPs ...
Arun Kejariwal, Alexander V. Veidenbaum, Alexandru...
ISCA
2012
IEEE
208views Hardware» more  ISCA 2012»
11 years 9 months ago
Harmony: Collection and analysis of parallel block vectors
Efficient execution of well-parallelized applications is central to performance in the multicore era. Program analysis tools support the hardware and software sides of this effor...
Melanie Kambadur, Kui Tang, Martha A. Kim
DSN
2007
IEEE
14 years 1 months ago
Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance
Transient faults are emerging as a critical concern in the reliability of general-purpose microprocessors. As architectural trends point towards multi-threaded multi-core designs,...
Alex Shye, Tipp Moseley, Vijay Janapa Reddi, Josep...