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» Executing Verified Compiler Specification
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DSN
2007
IEEE
14 years 1 months ago
BlackJack: Hard Error Detection with Redundant Threads on SMT
Testing is a difficult process that becomes more difficult with scaling. With smaller and faster devices, tolerance for errors shrinks and devices may act correctly under certain ...
Ethan Schuchman, T. N. Vijaykumar
TCAD
2008
101views more  TCAD 2008»
13 years 7 months ago
Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors
Functional correctness is a vital attribute of any hardware design. Unfortunately, due to extremely complex architectures, widespread components, such as microprocessors, are often...
Ilya Wagner, Valeria Bertacco, Todd M. Austin
ACSD
2010
IEEE
255views Hardware» more  ACSD 2010»
13 years 5 months ago
From POOSL to UPPAAL: Transformation and Quantitative Analysis
POOSL (Parallel Object-Oriented Specification Language) is a powerful general purpose system-level modeling language. In research on design space exploration of motion control syst...
Jiansheng Xing, Bart D. Theelen, Rom Langerak, Jac...
ICDE
2007
IEEE
127views Database» more  ICDE 2007»
14 years 9 months ago
Supporting Streaming Updates in an Active Data Warehouse
Active Data Warehousing has emerged as an alternative to conventional warehousing practices in order to meet the high demand of applications for up-to-date information. In a nutsh...
Neoklis Polyzotis, Spiros Skiadopoulos, Panos Vass...
EMSOFT
2007
Springer
14 years 1 months ago
Exploiting non-volatile RAM to enhance flash file system performance
Non-volatile RAM (NVRAM) such as PRAM (Phase-change RAM), FeRAM (Ferroelectric RAM), and MRAM (Magnetoresistive RAM) has characteristics of both non-volatile storage and random ac...
In Hwan Doh, Jongmoo Choi, Donghee Lee, Sam H. Noh