Sciweavers

3893 search results - page 32 / 779
» Execution Architectures and Compilation
Sort
View
DAC
2009
ACM
14 years 11 months ago
WCET-aware register allocation based on graph coloring
Current compilers lack precise timing models guiding their built-in optimizations. Hence, compilers apply ad-hoc heuristics during optimization to improve code quality. One of the...
Heiko Falk
WCRE
2002
IEEE
14 years 3 months ago
Register Liveness Analysis for Optimizing Dynamic Binary Translation
Dynamic binary translators compile machine code from a source architecture to a target architecture at run time. Due to the hard time constraints of just-in-time compilation only ...
Mark Probst, Andreas Krall, Bernhard Scholz
ASPLOS
1994
ACM
14 years 2 months ago
Reducing Branch Costs via Branch Alignment
Several researchers have proposed algorithms for basic block reordering. We call these branch alignment algorithms. The primary emphasis of these algorithms has been on improving ...
Brad Calder, Dirk Grunwald
IPPS
1999
IEEE
14 years 2 months ago
PARADIGM (version 2.0): A New HPF Compilation System
In this paper,a we present sample performance figures for a new linear algebra-based compilation framework implemented in a research HPF compiler called PARADIGM. The metrics cons...
Pramod G. Joisha, Prithviraj Banerjee
CROSSROADS
2008
86views more  CROSSROADS 2008»
13 years 10 months ago
The use of compiler optimizations for embedded systems software
O ptimizing embedded applications using a compiler can generally be broken down into two major categories: hand-optimizing code to take advantage of a particular processor's ...
Joe Bungo