453 search results - page 29 / 91 » Execution and Cache Performance of the Scheduled Dataflow Ar... |
CCGRID
2001
IEEE
13 years 11 months ago
2001
IEEE
High performance computing on parallel architectures currently uses different approaches depending on the hardory model of the architecture, the abstraction level of the programmi...
CAL
2002
13 years 7 months ago
2002
Embedded systems commonly execute one program for their lifetime. Designing embedded system architectures with configurable components, such that those components can be tuned to t...
WCET
2010
13 years 5 months ago
2010
Safe and tight worst-case execution times (WCETs) are important when scheduling hard realtime systems. This paper presents METAMOC, a modular method, based on model checking and s...
VLSID
2005
IEEE
14 years 8 months ago
2005
IEEE
An Application Specific Instruction Set Processor (ASIP) exploits special characteristics of the given application(s) to meet the desired performance, cost and power requirements....
ISCA
1994
IEEE
13 years 11 months ago
1994
IEEE
Multithreaded architectures context switch between instruction streams to hide memory access latency. Although this improves processor utilization, it can increase cache interfere...