453 search results - page 51 / 91 » Execution and Cache Performance of the Scheduled Dataflow Ar... |
CF
2004
ACM
14 years 2 months ago
2004
ACM
Current instruction fetch policies in SMT processors are oriented towards optimization of overall throughput and/or fairness. However, they provide no control over how individual ...
ECRTS
2007
IEEE
14 years 3 months ago
2007
IEEE
Of late, there has been a considerable interest in models, algorithms and methodologies specifically targeted towards designing hardware and software for streaming applications. ...
IPPS
1998
IEEE
14 years 1 months ago
1998
IEEE
In the study of PetaFlop project, Processor-In-Memory array was proposed to be a target architecture in achieving 1015 floating point operations per second computing performance. ...
IPCCC
2007
IEEE
14 years 3 months ago
2007
IEEE
As Chip Multiprocessor (CMP) has become the mainstream in processor architectures, Intel and AMD have introduced their dual-core processors to the PC market. In this paper, perfor...
PPAM
2007
Springer
14 years 3 months ago
2007
Springer
As multicore systems continue to gain ground in the High Performance Computing world, linear algebra algorithms have to be reformulated or new algorithms have to be developed in or...