453 search results - page 5 / 91 » Execution and Cache Performance of the Scheduled Dataflow Ar... |
HIPEAC
2009
Springer
13 years 11 months ago
2009
Springer
Abstract. Exposing more instruction-level parallelism in out-of-order superscalar processors requires increasing the number of dynamic in-flight instructions. However, large instru...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
Static worst-case execution time (WCET) analysis is done by modeling the hardware behavior. In this paper we describe a WCET analysis technique to analyze systems with function ca...
CODES
1999
IEEE
13 years 12 months ago
1999
IEEE
This paper presents an enhancement of our "Algorithm Architecture Adequation" (AAA) prototyping methodology which allows to rapidly develop and optimize the implementati...
ISCA
2009
IEEE
14 years 2 months ago
2009
IEEE
While microprocessor designers turn to multicore architectures to sustain performance expectations, the dramatic increase in parallelism of such architectures will put substantial...
IEEEPACT
2007
IEEE
14 years 1 months ago
2007
IEEE
Continued scaling of CMOS technology to smaller transistor sizes makes modern processors more susceptible to both transient and permanent hardware faults. Circuitlevel techniques ...