453 search results - page 66 / 91 » Execution and Cache Performance of the Scheduled Dataflow Ar... |
APCSAC
2001
IEEE
14 years 14 days ago
2001
IEEE
Java bytecodes can be executed with the following three methods: a Java interpretor running on a particular machine interprets bytecodes; a Just-In-Time (JIT) compiler translates ...
ICCD
2004
IEEE
14 years 5 months ago
2004
IEEE
Speculative Multi-Threading (SpMT) can improve single-threaded application performance using the multiple thread contexts available in current processors. We propose a minimal SpM...
MICRO
2005
IEEE
14 years 2 months ago
2005
IEEE
Conventional processors use a fully-associative store queue (SQ) to implement store-load forwarding. Associative search latency does not scale well to capacities and bandwidths re...
HPCA
2002
IEEE
14 years 9 months ago
2002
IEEE
Cyclops is a new architecture for high performance parallel computers being developed at the IBM T. J. Watson Research Center. The basic cell of this architecture is a single-chip...
IPPS
1998
IEEE
14 years 1 months ago
1998
IEEE
Instruction scheduling methods based on the construction of state diagrams (or automata) have been used for architectures involving deeply pipelined function units. However, the s...