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» Experiences in Hardware Trojan Design and Implementation
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RTAS
1997
IEEE
13 years 11 months ago
Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
ÐWith effective packet-scheduling mechanisms, modern integrated networks can support the diverse quality-of-service requirements of emerging applications. However, arbitrating bet...
Sung-Whan Moon, Kang G. Shin, Jennifer Rexford
FPL
2005
Springer
79views Hardware» more  FPL 2005»
14 years 1 months ago
FPGA-based implementation and comparison of recursive and iterative algorithms
The paper analyses and compares alternative iterative and recursive implementations of FPGA circuits for various problems. Two types of recursive calls have been examined, namely ...
Valery Sklyarov, Iouliia Skliarova, Bruno Figueire...
ASPLOS
2011
ACM
12 years 11 months ago
Hardware acceleration of transactional memory on commodity systems
The adoption of transactional memory is hindered by the high overhead of software transactional memory and the intrusive design changes required by previously proposed TM hardware...
Jared Casper, Tayo Oguntebi, Sungpack Hong, Nathan...
SPAA
2010
ACM
14 years 10 days ago
Simplifying concurrent algorithms by exploiting hardware transactional memory
We explore the potential of hardware transactional memory (HTM) to improve concurrent algorithms. We illustrate a number of use cases in which HTM enables significantly simpler c...
Dave Dice, Yossi Lev, Virendra J. Marathe, Mark Mo...
ICCCN
2008
IEEE
14 years 2 months ago
Sentinel: Hardware-Accelerated Mitigation of Bot-Based DDoS Attacks
—Effective defenses against DDoS attacks that deplete resources at the network and transport layers have been deployed commercially. Therefore, DDoS attacks increasingly use norm...
Peter Djalaliev, Muhammad Jamshed, Nicholas Farnan...