774 search results - page 41 / 155 » Experiences of low power design implementation and verificat... |
VLSID
2006
IEEE
14 years 9 months ago
2006
IEEE
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex d...
ISCAS
2006
IEEE
14 years 2 months ago
2006
IEEE
In this paper we present two polynomial time-complexity heuristic algorithms for optimization of gate-oxide leakage (tunneling current) during behavioral synthesis through simulta...
CDC
2009
IEEE
13 years 9 months ago
2009
IEEE
Abstract-- Formation control experiments are performed using two robots, each equipped with a camera. When both robots are fully informed of the reference velocity, a decentralized...
DAC
2005
ACM
13 years 10 months ago
2005
ACM
With 90nm CMOS in production and 65nm testing in progress, power has been pushed to the forefront of design metrics. This paper will outline practical techniques that are used to ...
FPGA
2009
ACM
14 years 3 months ago
2009
ACM
Modern Field Programmable Gate Arrays (FPGAs) are capable of performing complex discrete signal processing algorithms with clock rates above 100MHz. This combined with FPGA’s lo...