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GLVLSI
2007
IEEE
158views VLSI» more  GLVLSI 2007»
13 years 10 months ago
RT-level vector selection for realistic peak power simulation
We present a vector selection methodology for estimating the peak power dissipation in a CMOS logic circuit. The ultimate goal is to combine the speed of RT-level simulation with ...
Chia-Chien Weng, Ching-Shang Yang, Shi-Yu Huang
JEA
2008
120views more  JEA 2008»
13 years 8 months ago
Better external memory suffix array construction
Suffix arrays are a simple and powerful data structure for text processing that can be used for full text indexes, data compression, and many other applications in particular in b...
Roman Dementiev, Juha Kärkkäinen, Jens M...
LCN
2005
IEEE
14 years 2 months ago
Implementation and Performance Analysis of a Packet Scheduler on a Programmable Network Processor
— The problem of achieving fairness in the allocation of the bandwidth resource on a link shared by multiple flows of traffic has been extensively researched over the last deca...
Fariza Sabrina, Salil S. Kanhere, Sanjay Jha
SIGMOD
2005
ACM
156views Database» more  SIGMOD 2005»
14 years 9 months ago
Model-driven design of service-enabled web applications
Significant efforts are currently invested in application integration to enable the interaction and composition of business processes of different companies, yielding complex, mul...
Marco Brambilla, Stefano Ceri, Piero Fraternali, R...
HICSS
2006
IEEE
164views Biometrics» more  HICSS 2006»
14 years 2 months ago
A Methodology for Generating Application-Specific Heterogeneous Processor Arrays
Hardware designers are increasingly turning to Single Chip Multi-Processors to achieve power and throughput goals. To further increase performance for a specific application the c...
Stephen D. Craven, Cameron Patterson, Peter M. Ath...