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ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
14 years 6 months ago
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...
FPGA
2007
ACM
150views FPGA» more  FPGA 2007»
14 years 3 months ago
FPGA-friendly code compression for horizontal microcoded custom IPs
Shrinking time-to-market and high demand for productivity has driven traditional hardware designers to use design methodologies that start from high-level languages. However, meet...
Bita Gorjiara, Daniel Gajski
SENSYS
2006
ACM
14 years 3 months ago
Capturing high-frequency phenomena using a bandwidth-limited sensor network
Small-form-factor, low-power wireless sensors—motes—are convenient to deploy, but lack the bandwidth to capture and transmit raw high-frequency data, such as human voices or n...
Ben Greenstein, Christopher Mar, Alex Pesterev, Sh...
GLVLSI
2009
IEEE
158views VLSI» more  GLVLSI 2009»
14 years 27 days ago
Exploration of memory hierarchy configurations for efficient garbage collection on high-performance embedded systems
Modern embedded devices (e.g., PDAs, mobile phones) are now incorporating Java as a very popular implementation language in their designs. These new embedded systems include multi...
José Manuel Velasco, David Atienza, Katzali...
WWW
2006
ACM
14 years 9 months ago
The web structure of e-government - developing a methodology for quantitative evaluation
In this paper we describe preliminary work that examines whether statistical properties of the structure of websites can be an informative measure of their quality. We aim to deve...
Vaclav Petricek, Tobias Escher, Ingemar J. Cox, He...