− This paper presents an efficient system level power saving method for DRAM with multiple power modes. The proposed method is based on the power aware scheduling algorithm that ...
Modern high performance routers rely on sophisticated interconnection networks to meet ever increasing demands on capacity. Previous studies have used a combination of analysis an...
Charlie Wiseman, Jonathan S. Turner, Ken Wong, Bra...
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
—In this paper we propose two advanced algorithms which allow for both differentiated quality-of-service (QOS) and power conservation in input-queued packet switches. These algor...
Benjamin Yolken, Dimitrios Tsamis, Nicholas Bambos
We study a problem in which a single sensor is scheduled to observe sites periodically, motivated by applications in which the goal is to maintain up-to-date readings for all the o...
Yosef Alayev, Amotz Bar-Noy, Matthew P. Johnson, L...