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» Experiments with Parallelizing a Tribology Application
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ICPADS
2006
IEEE
14 years 1 months ago
Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture
The widening gap between processor and memory performance is the main bottleneck for modern computer systems to achieve high processor utilization. In this paper, we propose a new...
Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edw...
CCGRID
2005
IEEE
14 years 1 months ago
Q-SAC: toward QoS optimized service automatic composition
The emerging service grids bring together various distributed services to a ‘market’ for clients to request and enable the integration of services across distributed, heteroge...
Hanhua Chen, Hai Jin, Xiaoming Ning, Zhipeng Lu
ISESE
2005
IEEE
14 years 1 months ago
Empirical study design in the area of high-performance computing (HPC)
The development of High-Performance Computing (HPC) programs is crucial to progress in many fields of scientific endeavor. We have run initial studies of the productivity of HPC d...
Forrest Shull, Jeffrey Carver, Lorin Hochstein, Vi...
RTAS
2005
IEEE
14 years 1 months ago
VPN Gateways over Network Processors: Implementation and Evaluation
Networking applications, such as VPN and content filtering, demand extra computing power in order to meet the throughput requirement nowadays. In addition to pure ASIC solutions, ...
Yi-Neng Lin, Chiuan-Hung Lin, Ying-Dar Lin, Yuan-C...
DCOSS
2005
Springer
14 years 1 months ago
TARA: Thermal-Aware Routing Algorithm for Implanted Sensor Networks
Implanted biological sensors are a special class of wireless sensor networks that are used in-vivo for various medical applications. One of the major challenges of continuous in-vi...
Qinghui Tang, Naveen Tummala, Sandeep K. S. Gupta,...