375 search results - page 63 / 75 » Explicit gate delay model for timing evaluation |
INFOCOM
2005
IEEE
14 years 1 months ago
2005
IEEE
— Packet buffers in router/switch interfaces constitute a central element of packet networks. The appropriate sizing of these buffers is an important and open research problem. M...
INFOCOM
2002
IEEE
14 years 17 days ago
2002
IEEE
This paper concerns itself with the performance of deflection routing in optical burst-switched networks based on Just-Enough-Time (JET) signaling. Generally speaking, buffer requi...
BNCOD
2007
13 years 9 months ago
2007
This paper presents WordRank, a new page ranking system, which exploits similarity between interconnected pages. WordRank introduces the model of the ‘biased surfer’ which is ...
BMVC
2010
13 years 2 months ago
2010
View planning for three-dimensional (3D) reconstruction and inspection solves the problem of finding an efficient sequence of views allowing complete and high quality reconstructi...
EMSOFT
2006
Springer
13 years 11 months ago
2006
Springer
Bridging the gap between model-based design and platformbased implementation is one of the critical challenges for embedded software systems. In the context of embedded control sy...