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» Exploiting Architecture in Experimental System Development
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ASAP
2005
IEEE
169views Hardware» more  ASAP 2005»
14 years 3 months ago
Alleviating the Data Memory Bandwidth Bottleneck in Coarse-Grained Reconfigurable Arrays
It is widely known that parallel operation execution in multiprocessor systems generates a respective increase in memory accesses. Since the memory and bus subsystems provide a li...
Grigoris Dimitroulakos, Michalis D. Galanis, Costa...
P2P
2003
IEEE
110views Communications» more  P2P 2003»
14 years 3 months ago
Range Addressable Network: A P2P Cache Architecture for Data Ranges
Peer-to-peer computing paradigm is emerging as a scalable and robust model for sharing media objects. In this paper, we propose an architecture and describe the associated algorit...
Anshul Kothari, Divyakant Agrawal, Abhishek Gupta,...
MAM
2006
125views more  MAM 2006»
13 years 9 months ago
Stream computations organized for reconfigurable execution
Reconfigurable systems can offer the high spatial parallelism and fine-grained, bit-level resource control traditionally associated with hardware implementations, along with the f...
André DeHon, Yury Markovsky, Eylon Caspi, M...
ASE
1999
126views more  ASE 1999»
13 years 9 months ago
Behaviour Analysis of Distributed Systems Using the Tracta Approach
Behaviour analysis should form an integral part of the software development process. This is particularly important in the design of concurrent and distributed systems, where comp...
Dimitra Giannakopoulou, Jeff Kramer, Shing-Chi Che...
ASPLOS
2000
ACM
14 years 2 months ago
Architecture and design of AlphaServer GS320
This paper describes the architecture and implementation of the AlphaServer GS320, a cache-coherent non-uniform memory access multiprocessor developed at Compaq. The AlphaServer G...
Kourosh Gharachorloo, Madhu Sharma, Simon Steely, ...