87 search results - page 15 / 18 » Exploiting Instruction Redundancy for Transient Fault Tolera... |
DSD
2011
IEEE
12 years 7 months ago
2011
IEEE
—This paper presents an approach for the reliability-aware design optimization of real-time systems on multi-processor platforms. The optimization is based on an extension of wel...
ISCA
2007
IEEE
14 years 1 months ago
2007
IEEE
Transient faults due to particle strikes are a key challenge in microprocessor design. Driven by exponentially increasing transistor counts, per-chip faults are a growing burden. ...
ISCA
2007
IEEE
14 years 1 months ago
2007
IEEE
ACE analysis is a technique to provide an early reliability estimate for microprocessors. ACE analysis couples data from performance models with low level design details to identi...
MOBIHOC
2010
ACM
13 years 5 months ago
2010
ACM
In this paper, we address the problem of preserving generated data in a sensor network in case of node failures. We focus on the type of node failures that have explicit spatial s...
ICDCS
2000
IEEE
13 years 12 months ago
2000
IEEE
To assure dependable onboard evolution, we have developed a methodology called guarded software upgrading (GSU). In this paper, we focus on a low-cost approach to error containmen...