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» Exploiting Value Locality in Physical Register Files
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MAM
2008
114views more  MAM 2008»
13 years 8 months ago
Asymmetrically banked value-aware register files for low-energy and high-performance
Designing high-performance low-energy register files is of critical importance to the continuation of current performance advances in wide-issue and deeply pipelined superscalar m...
Shuai Wang, Hongyan Yang, Jie S. Hu, Sotirios G. Z...
PACS
2004
Springer
146views Hardware» more  PACS 2004»
14 years 2 months ago
An Optimized Front-End Physical Register File with Banking and Writeback Filtering
In recent years, processor manufacturers have converged on two types of register file architectures. Both IBM with its POWER series and Intel with its Pentium series are using a ...
Miquel Pericàs, Rubén Gonzále...
ASAP
2004
IEEE
101views Hardware» more  ASAP 2004»
14 years 15 days ago
Register Organization for Enhanced On-Chip Parallelism
Large register file with multiple ports is a critical component of a high-performance processor. A large number of registers are necessary for processing a larger number of in-fli...
Rama Sangireddy
HPCA
1998
IEEE
14 years 1 months ago
Virtual-Physical Registers
A novel dynamic register renaming approach is proposed in this work. The key idea of the novel scheme is to delay the allocation of physical registers until a late stage in the pi...
Antonio González, José Gonzál...
MICRO
1997
IEEE
127views Hardware» more  MICRO 1997»
14 years 29 days ago
Exploiting Dead Value Information
We describe Dead Value Information (DVI) and introduce three new optimizations which exploit it. DVI provides assertions that certain register values are dead, meaning they will n...
Milo M. K. Martin, Amir Roth, Charles N. Fischer