40 search results - page 5 / 8 » Exploiting Value Locality in Physical Register Files |
HPCA
2004
IEEE
14 years 9 months ago
2004
IEEE
Many current programmable architectures designed to exploit data parallelism require computation to be structured to operate on sequentially accessed vectors or streams of data. A...
IPPS
2007
IEEE
14 years 3 months ago
2007
IEEE
This paper proposes and evaluates a new microarchitecture for out-of-order processors that supports speculative renaming. We call speculative renaming to the speculative omission ...
SBACPAD
2008
IEEE
14 years 3 months ago
2008
IEEE
The performance impact of the Physical Register File (PRF) size on Simultaneous Multithreading processors has not been extensively studied in spite of being a critical shared reso...
ARCS
2010
Springer
14 years 3 months ago
2010
Springer
Register renaming is a widely used technique to remove false data dependencies in superscalar datapaths. Rename logic consists of a table that holds a physical register mapping for...
ISCA
2002
IEEE
14 years 1 months ago
2002
IEEE
An instruction set architecture (ISA) suitable for future microprocessor design constraints is proposed. The ISA has hierarchical register files with a small number of accumulator...