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» Exploiting Vector Parallelism in Software Pipelined Loops
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POPL
2010
ACM
14 years 4 months ago
A simple, verified validator for software pipelining
Software pipelining is a loop optimization that overlaps the execution of several iterations of a loop to expose more instruction-level parallelism. It can result in first-class p...
Jean-Baptiste Tristan, Xavier Leroy
LCTRTS
2005
Springer
14 years 1 months ago
Complementing software pipelining with software thread integration
Software pipelining is a critical optimization for producing efficient code for VLIW/EPIC and superscalar processors in highperformance embedded applications such as digital sign...
Won So, Alexander G. Dean
FPL
2009
Springer
117views Hardware» more  FPL 2009»
14 years 4 days ago
Data parallel FPGA workloads: Software versus hardware
Commercial soft processors are unable to effectively exploit the data parallelism present in many embedded systems workloads, requiring FPGA designers to exploit it (laboriously) ...
Peter Yiannacouras, J. Gregory Steffan, Jonathan R...
IPPS
2000
IEEE
13 years 12 months ago
JavaSpMT: A Speculative Thread Pipelining Parallelization Model for Java Programs
This paper presents a new approach to improve performance of Java programs by extending the superthreaded speculative execution model [14, 15] to exploit coarsegrained parallelism...
Iffat H. Kazi, David J. Lilja
LCPC
1993
Springer
13 years 11 months ago
Maximizing Loop Parallelism and Improving Data Locality via Loop Fusion and Distribution
Abstract. Loop fusion is a program transformation that merges multiple loops into one. It is e ective for reducing the synchronization overhead of parallel loops and for improving ...
Ken Kennedy, Kathryn S. McKinley