Sciweavers

110 search results - page 9 / 22
» Exploiting Vector Parallelism in Software Pipelined Loops
Sort
View
CGO
2003
IEEE
14 years 25 days ago
Optimizing Memory Accesses For Spatial Computation
In this paper we present the internal representation and optimizations used by the CASH compiler for improving the memory parallelism of pointer-based programs. CASH uses an SSA-b...
Mihai Budiu, Seth Copen Goldstein
IPPS
2005
IEEE
14 years 1 months ago
Control-Flow Independence Reuse via Dynamic Vectorization
Current processors exploit out-of-order execution and branch prediction to improve instruction level parallelism. When a branch prediction is wrong, processors flush the pipeline ...
Alex Pajuelo, Antonio González, Mateo Valer...
FCCM
2000
IEEE
122views VLSI» more  FCCM 2000»
13 years 12 months ago
Evaluating Hardware Compilation Techniques
Hardware compilation techniques which use highlevel programming languages to describe and synthesize hardware are gaining popularity. They are especially useful for reconfigurable...
Markus Weinhardt, Wayne Luk
JMLR
2006
105views more  JMLR 2006»
13 years 7 months ago
Parallel Software for Training Large Scale Support Vector Machines on Multiprocessor Systems
Parallel software for solving the quadratic program arising in training support vector machines for classification problems is introduced. The software implements an iterative dec...
Luca Zanni, Thomas Serafini, Gaetano Zanghirati
SPAA
2000
ACM
13 years 12 months ago
Algorithmic foundations for a parallel vector access memory system
This paper presents mathematical foundations for the design of a memory controller subcomponent that helps to bridge the processor/memory performance gap for applications with str...
Binu K. Mathew, Sally A. McKee, John B. Carter, Al...