9 search results - page 1 / 2 » Exploiting inter-thread temporal locality for chip multithre... |
IPPS
2010
IEEE
13 years 8 months ago
2010
IEEE
Multi-core organizations increasingly support multiple threads per core. Threads on a core usually share a single first-level data cache, so thread schedulers must try to minimize ...
HIPEAC
2011
Springer
12 years 10 months ago
2011
Springer
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
IPPS
2006
IEEE
14 years 5 months ago
2006
IEEE
FPGA chips in reconfigurable computer systems are used as malleable coprocessors where components of a hardware library of functions can be configured as needed. As the number of ...
HPCS
2002
IEEE
14 years 3 months ago
2002
IEEE
Thread migration is one approach to remote memory accesses on distributed memory parallel computers. In thread migration, threads of control migrate between processors to access d...
ASPLOS
2008
ACM
14 years 28 days ago
2008
ACM
The recent shift in the industry towards chip multiprocessor (CMP) designs has brought the need for multi-threaded applications to mainstream computing. As observed in several lim...