Sciweavers

148 search results - page 28 / 30
» Exploiting regularity for low-power design
Sort
View
CASES
2009
ACM
14 years 1 months ago
CheckerCore: enhancing an FPGA soft core to capture worst-case execution times
Embedded processors have become increasingly complex, resulting in variable execution behavior and reduced timing predictability. On such processors, safe timing specifications e...
Jin Ouyang, Raghuveer Raghavendra, Sibin Mohan, Ta...
IJCNN
2007
IEEE
14 years 1 months ago
Agnostic Learning vs. Prior Knowledge Challenge
We organized a challenge for IJCNN 2007 to assess the added value of prior domain knowledge in machine learning. Most commercial data mining programs accept data pre-formatted in ...
Isabelle Guyon, Amir Saffari, Gideon Dror, Gavin C...
ISCA
2007
IEEE
198views Hardware» more  ISCA 2007»
14 years 1 months ago
Making the fast case common and the uncommon case simple in unbounded transactional memory
Hardware transactional memory has great potential to simplify the creation of correct and efficient multithreaded programs, allowing programmers to exploit more effectively the s...
Colin Blundell, Joe Devietti, E. Christopher Lewis...
ISVLSI
2005
IEEE
169views VLSI» more  ISVLSI 2005»
14 years 1 months ago
High Performance Array Processor for Video Decoding
high NRE cost. Therefore, general purpose programmable processors using software to perform various functions become more attractive since programmability can simplify system devel...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin
LCTRTS
2005
Springer
14 years 27 days ago
Cache aware optimization of stream programs
Effective use of the memory hierarchy is critical for achieving high performance on embedded systems. We focus on the class of streaming applications, which is increasingly preval...
Janis Sermulins, William Thies, Rodric M. Rabbah, ...