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IJNSEC
2007
137views more  IJNSEC 2007»
13 years 7 months ago
An FPGA-based AES-CCM Crypto Core For IEEE 802.11i Architecture
The widespread adoption of IEEE 802.11 wireless networks has brought its security paradigm under active research. One of the important research areas in this field is the realiza...
Arshad Aziz, Nassar Ikram
GLVLSI
2007
IEEE
115views VLSI» more  GLVLSI 2007»
14 years 1 months ago
Novel architectures for efficient (m, n) parallel counters
Parallel counters are key elements in many arithmetic circuits, especially fast multipliers. In this paper, novel architectures and designs for high speed, low power (3, 2), (7, 3...
Sreehari Veeramachaneni, Lingamneni Avinash, Kirth...
ARCS
2004
Springer
13 years 11 months ago
STAFF: State Transition Applied Fast Flash Translation Layer
Abstract. Recently, flash memory is widely used in embedded applications since it has strong points: non-volatility, fast access speed, shock resistance, and low power consumption....
Tae-Sun Chung, Stein Park, Myung-Jin Jung, Bumsoo ...
DAC
1995
ACM
13 years 11 months ago
Efficient Power Estimation for Highly Correlated Input Streams
- Power estimation in combinational modules is addressed from a probabilistic point of view. The zero-delay hypothesis is considered and under highly correlated input streams, the ...
Radu Marculescu, Diana Marculescu, Massoud Pedram
CF
2005
ACM
13 years 9 months ago
An efficient wakeup design for energy reduction in high-performance superscalar processors
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
Kuo-Su Hsiao, Chung-Ho Chen