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» FPGA technology mapping: a study of optimality
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TC
2011
13 years 2 months ago
Maximizing Spare Utilization by Virtually Reorganizing Faulty Cache Lines
—Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Since a large fraction of chip area is devoted to on-...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...
ESTIMEDIA
2009
Springer
13 years 5 months ago
Inter-kernel data reuse and pipelining on chip-multiprocessors for multimedia applications
The increasing demand for low power and high performance multimedia embedded systems has motivated the need for effective solutions to satisfy application bandwidth and latency req...
Luis Angel D. Bathen, Yongjin Ahn, Nikil D. Dutt, ...
CORR
2010
Springer
186views Education» more  CORR 2010»
13 years 2 months ago
QoS Routing in Smart Grid
Smart grid is an emerging technology which is able to control the power load via price signaling. The communication between the power supplier and power customers is a key issue in...
Husheng Li, Weiyi Zhang
ASAP
1997
IEEE
107views Hardware» more  ASAP 1997»
13 years 11 months ago
Tiling with limited resources
In the framework of perfect loop nests with uniform dependences, tiling has been extensively studied as a source-to-source program transformation. Little work has been devoted to ...
Pierre-Yves Calland, Jack Dongarra, Yves Robert
GECCO
2008
Springer
135views Optimization» more  GECCO 2008»
13 years 8 months ago
Agent-based support for interactive search in conceptual software engineering design
While recent attempts to search a conceptual software engineering design search space with multi-objective evolutionary algorithms have yielded promising results, the practical ap...
Christopher L. Simons, Ian C. Parmee