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ASPDAC
2001
ACM
137views Hardware» more  ASPDAC 2001»
14 years 6 days ago
Optimized address assignment for DSPs with SIMD memory accesses
This paper deals with address assignment in code generation for digital signal processors (DSPs) with SIMD (single instruction multiple data) memory accesses. In these processors ...
Markus Lorenz, David Koffmann, Steven Bashford, Ra...
CODES
2006
IEEE
14 years 2 months ago
Retargetable code optimization with SIMD instructions
Retargetable C compilers are nowadays widely used to quickly obtain compiler support for new embedded processors and to perform early processor architecture exploration. One frequ...
Manuel Hohenauer, Christoph Schumacher, Rainer Leu...
CC
2008
Springer
144views System Software» more  CC 2008»
13 years 10 months ago
Control Flow Emulation on Tiled SIMD Architectures
Heterogeneous multi-core and streaming architectures such as the GPU, Cell, ClearSpeed, and Imagine processors have better power/ performance ratios and memory bandwidth than tradi...
Ghulam Lashari, Ondrej Lhoták, Michael McCo...
DAMON
2009
Springer
14 years 3 months ago
Frequent itemset mining on graphics processors
We present two efficient Apriori implementations of Frequent Itemset Mining (FIM) that utilize new-generation graphics processing units (GPUs). Our implementations take advantage ...
Wenbin Fang, Mian Lu, Xiangye Xiao, Bingsheng He, ...
FPL
2008
Springer
119views Hardware» more  FPL 2008»
13 years 10 months ago
An FPGA-based high-speed, low-latency trigger processor for high-energy physics
An example of an FPGA based application for a high-energy physics experiment is presented which features all facets of modern FPGA design. The special requirements here are high b...
Jan de Cuveland, Felix Rettig, Venelin Angelov, Vo...