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ICCTA
2007
IEEE
14 years 1 months ago
Register Sharing Verification During Data-Path Synthesis
The variables of the high-level specifications and the automatically generated temporary variables are mapped on to the data-path registers during data-path synthesis phase of hig...
Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sa...
ACSD
2004
IEEE
113views Hardware» more  ACSD 2004»
14 years 1 months ago
Logic Synthesis for Asynchronous Circuits Based on Petri Net Unfoldings and Incremental SAT
The behaviour of asynchronous circuits is often described by Signal Transition Graphs (STGs), which are Petri nets whose transitions are interpreted as rising and falling edges of...
Victor Khomenko, Maciej Koutny, Alexandre Yakovlev
FORMATS
2006
Springer
14 years 1 months ago
Temporal Logic Verification Using Simulation
In this paper, we consider a novel approach to the temporal logic verification problem of continuous dynamical systems. Our methodology has the distinctive feature that enables the...
Georgios E. Fainekos, Antoine Girard, George J. Pa...
FSTTCS
2006
Springer
14 years 1 months ago
Branching Pushdown Tree Automata
We observe that pushdown tree automata (PTAs) known in the literature cannot express combinations of branching and pushdown properties. This is because a PTA processes the children...
Rajeev Alur, Swarat Chaudhuri
GECCO
2006
Springer
185views Optimization» more  GECCO 2006»
14 years 1 months ago
Memory analysis and significance test for agent behaviours
Many agent problems in a grid world have a restricted sensory information and motor actions. The environmental conditions need dynamic processing of internal memory. In this paper...
DaeEun Kim