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ITC
1999
IEEE
105views Hardware» more  ITC 1999»
14 years 1 months ago
Finite state machine synthesis with concurrent error detection
A new synthesis technique for designing finite state machines with on-line parity checking is presented. The output logic and the next-state logic of the finite state machines are...
Chaohuang Zeng, Nirmal R. Saxena, Edward J. McClus...
COLING
1994
13 years 10 months ago
Two Parsing Algorithms by Means of Finite State Transducers
We present a new apl)roach , ilhlstrated by two algorithms> for parsing not only Finite SI.ate (:Iranlnlars but also Context Free Grainlnars and their extension, by means of fi...
Emmanuel Roche
FPL
2000
Springer
155views Hardware» more  FPL 2000»
14 years 10 days ago
Synthesis and Implementation of RAM-Based Finite State Machines in FPGAs
This paper discusses the design and implementation of finite state machines (FSM) with combinational circuits that are built primarily from RAM blocks. It suggests a novel state as...
Valery Sklyarov
ISCAS
2002
IEEE
125views Hardware» more  ISCAS 2002»
14 years 1 months ago
Switching activity estimation of finite state machines for low power synthesis
A technique for computing the switching activity of synchronous Finite State Machine (FSM) implementations including the influence of temporal correlation among the next state si...
Mikael Kerttu, Per Lindgren, Mitchell A. Thornton,...
DAC
1994
ACM
14 years 25 days ago
BDD Variable Ordering for Interacting Finite State Machines
We address the problem of obtaining good variable orderings for the BDD representation of a system of interacting finite state machines (FSMs). Orderings are derived from the comm...
Adnan Aziz, Serdar Tasiran, Robert K. Brayton