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ISCA
2002
IEEE
82views Hardware» more  ISCA 2002»
14 years 19 days ago
Increasing Processor Performance by Implementing Deeper Pipelines
One architectural method for increasing processor performance involves increasing the frequency by implementing deeper pipelines. This paper will explore the relationship between ...
Eric Sprangle, Doug Carmean
19
Voted
JMM2
2007
118views more  JMM2 2007»
13 years 7 months ago
FPGA-based Real-time Optical Flow Algorithm Design and Implementation
—Optical flow algorithms are difficult to apply to robotic vision applications in practice because of their extremely high computational and frame rate requirements. In most case...
Zhaoyi Wei, Dah-Jye Lee, Brent E. Nelson
AHS
2007
IEEE
215views Hardware» more  AHS 2007»
13 years 7 months ago
Online Evolution for a High-Speed Image Recognition System Implemented On a Virtex-II Pro FPGA
Online incremental evolution for a complex high-speed pattern recognition architecture has been implemented on a Xilinx Virtex-II Pro FPGA. The fitness evaluation module is entir...
Kyrre Glette, Jim Torresen, Moritoshi Yasunaga
OSDI
1994
ACM
13 years 9 months ago
PathFinder: A Pattern-Based Packet Classifier
This paper describes a pattern-based approach to building packet classifiers. One novelty of the approach is that it can be implemented efficiently in both software and hardware. ...
Mary L. Bailey, Burra Gopal, Michael A. Pagels, La...
ICCD
2000
IEEE
106views Hardware» more  ICCD 2000»
14 years 3 days ago
Fast Subword Permutation Instructions Using Omega and Flip Network Stages
This paper proposes a new way of efficiently doing arbitrary ¢ -bit permutations in programmable processors modeled on the theory of omega and flip networks. The new omflip ins...
Xiao Yang, Ruby B. Lee