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FPGA
2009
ACM
482views FPGA» more  FPGA 2009»
14 years 10 days ago
A 17ps time-to-digital converter implemented in 65nm FPGA technology
This paper presents a new architecture for time-to-digital conversion enabling a time resolution of 17ps over a range of 50ns with a conversion rate of 20MS/s. The proposed archit...
Claudio Favi, Edoardo Charbon
CVIU
2010
115views more  CVIU 2010»
13 years 7 months ago
A modified model for the Lobula Giant Movement Detector and its FPGA implementation
Bio-inspired vision sensors are particularly appropriate candidates for navigation of vehicles or mobile robots due to their computational simplicity, allowing compact hardware im...
Hongying Meng, Kofi Appiah, Shigang Yue, Andrew Hu...
ACSAC
1999
IEEE
14 years 1 days ago
A Parallel Packet Screen for High Speed Networks
This paper demonstrates why security issues related to the continually increasing bandwidth of High Speed Networks (HSN) cannot be addressed with conventional firewall mechanisms....
Carsten Benecke
ISCAS
2008
IEEE
147views Hardware» more  ISCAS 2008»
14 years 2 months ago
Fast frequency acquisition all-digital PLL using PVT calibration
—Fast frequency acquisition is crucial for phase-locked loops (PLLs) used in portable devices, as on-chip clocks are frequently scaled down or up in order to manage power consump...
Hae-Soo Jeon, Duk-Hyun You, In-Cheol Park
DATE
1997
IEEE
99views Hardware» more  DATE 1997»
13 years 12 months ago
Fast controllers for data dominated applications
A target structure for implementing fast edge-triggered control units is presented. In many cases, the proposed controller is faster than a one-hot encoded structure as its correc...
Andre Hertwig, Hans-Joachim Wunderlich