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IEEEPACT
2002
IEEE
14 years 2 months ago
Speculative Alias Analysis for Executable Code
Optimizations performed at link time or directly applied to final program executables have received increased attention in recent years. Such low-level optimizations can benefit...
Manel Fernández, Roger Espasa
SPAA
2004
ACM
14 years 3 months ago
The potential in energy efficiency of a speculative chip-multiprocessor
While lower supply voltage is effective for energy reduction, it suffers performance loss. To mitigate the loss, we propose to execute only the part, which does not have any influ...
Yuu Tanaka, Toshinori Sato, Takenori Koushiro
ICS
2009
Tsinghua U.
14 years 4 months ago
Combining thread level speculation helper threads and runahead execution
With the current trend toward multicore architectures, improved execution performance can no longer be obtained via traditional single-thread instruction level parallelism (ILP), ...
Polychronis Xekalakis, Nikolas Ioannou, Marcelo Ci...
IEEEPACT
2002
IEEE
14 years 2 months ago
Cost Effective Memory Dependence Prediction using Speculation Levels and Color Sets
Memory dependence prediction allows out-of-order issue processors to achieve high degrees of instruction level parallelism by issuing load instructions at the earliest time withou...
Soner Önder
MICRO
1997
IEEE
108views Hardware» more  MICRO 1997»
14 years 2 months ago
Improving the Accuracy and Performance of Memory Communication Through Renaming
As processors continue to exploit more instruction level parallelism, a greater demand is placed on reducing the e ects of memory access latency. In this paper, we introduce a nov...
Gary S. Tyson, Todd M. Austin